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description the A8501 is a multioutput wled/rgb driver for backlighting medium-size displays. the A8501 integrates a boost converter and four 100 ma current sinks. led channels can be tied together for up to 400 ma sink capability. it can work from a single power supply of 8 to 21 v and withstand up to 40 v. the boost converter is a constant frequency, current-mode converter. operating frequency can be set to 2 mhz in order to avoid interference with the am radio band. the integrated boost dmos switch is rated for 40 v at 3.6 a. pwm dimming allows led currents to be controlled at up to a 1000:1 ratio. additional 4:1 dimming can be achieved by using the dim pin. the A8501 provides protection against output connector shorts through an integrated output disconnect switch. an optional external thermistor can be used to limit led current based on panel temperature. the device is supplied in a surface mount, 28-pin tssop package (suffix lp), with exposed thermal pad for enhanced thermal dissipation. it is lead (pb) free, with a leadframe plating choice of 100% matte-tin (suffix t) or tin-bismuth (suffix b). applications include: ? gps navigation systems ? automotive infotainment ? back-up camera displays ? cluster backlighting ? portable dvd players ? industrial lcd displays 8501-ds, rev.3 features and benefits ? 600 khz to 2.2 mhz switching frequency?ability to operate above the am band ? internal bias supply for single-supply operation (v in = 8 to 21 v) ? boost converter with integrated 40 v dmos switch and ovp?load-dump protection ? 3.5 a shutdown current?limits battery drain ? active current sharing between led strings for 0.8% current matching and 0.7% accuracy ? drive up to 9 series leds in 4 parallel strings, 36 leds maximum (v f = 3.5 v, i f = 100 ma) ? led sinks rated for 100 ma each (400 ma total) ? pwm dimming with led pwm duty cycle control ? 4000:1 dimming range ? extensive fault mode protection schemes: ? shorted led protection against misconnected loads? with true output disconnect ? open led disconnect protects against led failures ? external thermistor sensing to limit led temperature ? output overvoltage protection (ovp): 19.5 v default can be adjusted as high as 38 v ? open schottky and open ovp resistor protection against external component failure ? input under- and overvoltage protection (uvlo and ovlo) against v in variation ? boost current limit, output short circuit limit, overtemperature protection (otp), and soft start 2 mhz , 4 channel100 ma wled/rgb driver with output disconnect package: typical application not to scale A8501 fset nc pad vto vti comp iset riset rvc ntc optional configuration for thermal derating ?t d1 l1 10 h rfset vin sw sw sw ovp cap out rovp 78.7 k 25.5 k 24.3 k v bat 8 to 21 v A8501 A8501 led4 led3 led2 led1 dim en sel1 sel2 bias ccomp 1 f 10 v cout 4.7 f 50 v cin cbat 4.7 f 35 v cbias 0.1 f 10 v vto vti dgnd lgnd agnd pgnd pgnd pgnd 28-pin tssop with exposed thermal pad (package lp) figure 1. lcd monitor backlight driving 4 led strings. on/off and dimming control using enable pin. ? current = 50 ma per string ? ovp = 35 v nominal ? switching frequency = 2 mhz
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number operating temperature, t a packing package leadframe plating A8501elptr-t ?40c to 85c 4000 pieces per 13-in. reel 28-pin tssop with exposed thermal pad 100% matte tin A8501glptr-t ?40c to 105c 4000 pieces per 13-in. reel 28-pin tssop with exposed thermal pad 100% matte tin A8501klptr-b ?40c to 125c 4000 pieces per 13-in. reel 28-pin tssop with exposed thermal pad tin-bismuth A8501klptr-t ?40c to 125c 4000 pieces per 13-in. reel 28-pin tssop with exposed thermal pad 100% matte tin absolute maximum ratings* characteristic symbol notes rating units sw, ovp, cap, out pins ?0.3 to 40 v led1 through led4 pins ?0.3 to 21 v vin pin v in steady state ?0.3 to 34 v transient < 1 s 40 v dim pin v dim ?0.3 to 6 v remaining pins ?0.3 to 7 v operating ambient temperature t a range e ?40 to 85 oc range g ?40 to 105 oc range k ?40 to 125 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc *stresses beyond those listed in this table may cause permanent damage to the device. the absolute maximum ratings are stress r atings only, and functional operation of the device at these or any other conditions beyond those indicated in the electrical characte ristics table is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. thermal characteristics characteristic symbol test conditions* value units package thermal resistance r ja 4-layer pcb based on jedec standard 28 oc/w *additional thermal information available on allegro website.
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pgnd pgnd pgnd agnd bias led1 open led detect and disconnect shorted led detect led3 dgnd lgnd comp vin sw out led4 led2 sel1 sel2 en vto vti iset ovp fault references 100 k 100 k device control internal supply feedback control charge pump overcurrent comparators overvoltage comparators boost regulator bias supply + ? pgnd current sinks led current reference + ? minimum select 2.46 v 1.23 v dim fset osc sw sw ovp cap 2 4 pad functional block diagram
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagram bias dgnd dim sw sw sw ovp cap agnd iset vti vto led1 led2 en sel2 sel1 pgnd pgnd pgnd nc vin comp fset out led4 led3 lgnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pad terminal list table number name function 1 bias output of internal 6 v bias supply. decouple with a 0.1 f ceramic capacitor to dgnd. 2 dgnd digital signal ground. connect agnd, dgnd, lgnd, pgnd, and pad using star ground connection. 3 dim sets i led by adjusting the i set to i ledx current gain, a iset . when dim = v il , a iset = 960 and when dim=v ih , a iset = 240. 4, 5, 6 sw dmos switch drain node. tie these three pins together on the pcb. 7 ovp to enable overvoltage protection, connect this pin through a resistor to the cap pin. the default ovp level, with 0 resistor, is 19.5 v. external resistor can set ovp up to 38 v. 8 cap input connection for output disconnect switch. 9 agnd analog signal ground. connect agnd, dgnd, lgnd, pgnd, and pad using star ground connection. 10 iset sets the 100% current level through led strings. set by value of riset connected between iset and agnd. 11 vti iset voltage override. sets the iset voltage when v ti < 1.23 v. tie directly to vto pin to disable this feature. this pin can be used for led current thermal derating or external analog led current control. see the typical application circuits section for additional information. 12 vto 2.46 v output voltage. use this voltage to bias an external ntc resistor or as a dac reference. this pin can be used as a logic high signal for the sel and dim pins. 13,14,16,17 ledx led current sinks. 15 lgnd power ground for led current sinks. connect agnd, dgnd, lgnd, pgnd, and pad using star ground connection. 18 out output connection for output disconnect switch. connect led common connection to this pin. 19 fset connect rfset between fset and agnd to set boost switching frequency. 20 comp sets boost loop compensation. connect external compensation capacitor between comp and agnd for boost converter stability . 21 vin input supply for the device. decouple with a 0.1 f ceramic capacitor. 22 nc not connected internally. it is recommended to connect this pin to external ground. 23, 24, 25 pgnd power ground. connect agnd, dgnd, lgnd, pgnd, and pad using star ground connection. 26 sel1 sel1 and sel2 together select which led strings are enabled. see functional description section. 27 sel2 28 en enable and pwm led current control. apply logic-level pwm for pwm-controlled dimming mode. ?pad exposed thermal pad. connect agnd, dgnd, lgnd, pgnd, and pad using star ground connection. connect to pcb copper layer for enhanced heat dissipation.
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics valid using circuit shown in figure 1; v in = 12 v, en = sel1 = sel2 =5 v, r iset = 12.4 k , r fset = 24.3 k , vto shorted to vti guaranteed over the full operating temperature range with t a =t j , typical specifications are at t a = 25oc; unless otherwise noted characteristics symbol test conditions min. typ. max. unit general input voltage range v in 8 ? 21 v undervoltage lockout threshold v uvlo(th) v in falling 5.7 6.5 6.8 v uvlo hysteresis window v uvlo(hys) 0.21 0.55 0.81 v overvoltage lockout threshold v ovlo(th) v in rising 29 32 34 v supply current i s 2 mhz switching at no load 4 11 15 ma en = v il , in shutdown, t a = 25c, cap = vin = sw = ovp = 16 v i s = i vin + i sw + i cap + i ovp ? 3.5 6 a en = v il , in shutdown, t a = ?40c to 125c, cap = vin = sw = ovp = 16 v, i s = i vin + i sw + i cap + i ovp ? 3.5 10 a en = v il , not in shutdown, i s = i vin ?24ma logic input levels (dim, en, selx pins) input voltage level-low v il ? ? 0.4 v input voltage level-high v ih 1.5 ? ? v input leakage current (en, dim pins) i lkg1 v dim , v en = 5 v 30 50 70 a input leakage current (selx pins) i lkg2 v selx = 5 v ? ? 1 a overvoltage protection output overvoltage threshold v ovp(th) ovp pin connected to out pin 18 19.5 21 v ovp sense current i ovph 183 200 217 a ovp leakage current i ovp(lkg) v ovp = 18 v, en = v il , in shutdown ? 0.1 1 a boost switch switch on resistance r swds(on) i sw = 2 a 40 100 300 m switch leakage current i sw(lkg) v sw = 21 v ? 0.1 10 a switch current limit i sw(lim) 3 3.6 5.3 a led current sinks ledx regulation voltage v led v led1 = v led2 = v led3 = v led4 ? 750 1100 mv i iset to i ledx current gain a iset i iset = 100 a, dim = v il 914 960 1008 a/a i iset = 100 a, dim= v ih 228 240 252 a/a iset pin voltage v iset 1.13 1.235 1.34 v vto pin voltage v to i vto = 1 ma 2.00 2.46 2.65 v vto pin current maximum i to(max) i vto increased until v to drops by 1% 1.5 2.4 5 ma vti pin voltage v ti(falling) v ti start >1.34 v, vti pin voltage decreasing before control changes to vti pin 1.00 1.12 1.23 v v ti(rising) v ti start <1 v vti pin increasing before changing to internal reference 1.13 1.235 1.34 v iset pin allowable current range i iset 20 ? 100 a continued on the next page?
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued) valid using circuit shown in figure 1; v in = 12 v, en = sel1 = sel2 =5 v, r iset = 12.4 k , r fset = 24.3 k , vto shorted to vti , guaranteed over the full operating temperature range with t a =t j , typical specifications are at t a = 25oc; unless otherwise noted characteristics symbol test conditions min. typ. max. unit ledx accuracy 1 err led riset = 12.4 k . 100% current ratio, measured as the average of v ledx , for led1 through led4, with v ledx = 0.75 v, t a =t j = 0 to 125c ? 0.7 3 % ledx matching 2 ? ledx i iset = 100 a, 100% current ratio, with v ledx = 0.75 v ? 0.8 3 % led switch leakage current i s(lkg) v ledx = 17.5 v, en = v il = 0 v 4.8 8.75 12.8 a ledx short detect voltage threshold v ledsc on any ledx pin, forces latched shutdown 17.5 19 21 v output disconnect switch on-resistance r ods(on) v in = 8 v, i out = 400 ma, t j = 125c ? 2 4 oscillator fset pin voltage v fset r fset = 24.3 k 1.14 1.235 1.33 v frequency f osc r fset = 24.3 k 1.8 2.1 2.4 mhz r fset = 51.1 k 0.850 1 1.285 mhz r fset = 84.5 k 0.5 0.6 0.8 mhz minimum switch off-time t off(min) ? 60 110 ns minimum switch on-time t on(min) ? 60 110 ns soft start soft start boost current limit i swss(lim) initial soft start current for boost switch 0.4 0.6 0.75 a soft start ledx current i ledss current through each enabled ledx pin during soft start, r iset =12.4 k 3 5 10 ma pwm timing on en pin maximum pwm dimming off-time t pwml measured while en = low, during dimming control, and internal references are powered on (exceeding t pwml results in shutdown) ? 131,072 ? f sw cycles minimum pwm on-time t pwmh ??6 s pwm high to led on delay t dpwm(on) time between pwm enable and when led current reaches 90% of maximum, with internal references enabled and t pwml not exceeded ?3? s pwm low to led off delay t dpwm(off) time between en going low and when led current reaches 10% of maximum, with internal references enabled and t pwml not exceeded ? 0.5 ? s thermal shutdown threshold 3 t tsd device temperature rising 150 172 195 c thermal shutdown hysteresis 3 t tsd(hys) 15 20 25 c 1 led accuracy is defined as (i iset 960 ? i led (av)) / (i iset 960), i led (av) measured as the average of i led1 through i led4 . 2 led current matching is defined as (i ledx ? i led (av)) / i led (av), with i led (av) as defined in footnote 1. 3 guaranteed by design and characterization, functional tested in production.
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com performance characteristics electrostatic discharge structures equivalent esd on pins 60 v vin vbias vin / vbias 7 v dgnd 6 v 100 k dim dim dgnd 35 v vin fset vin / fset 10 v dgnd 23 v ledx ledx dgnd 40 v 40 v cap cap / out out dgnd 40 to 60 v sw sw dgnd xgnd agnd, lgnd, pgnd, and dgnd dgnd dgnd pgnd 12 v 6 v iset 12 v 12 v 12 v 12 v 12 v vto vti iset, vto, and vti sel1, sel2, and en dgnd 6 v sel1 sel2 en 44 v ovp ovp 7 v comp comp dgnd
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com symbol parameter units/division c1 v bat 5 v c2 v out 20 v c3 i out 500 ma c4 i bat 500 ma t time 20 ms performance characteristics pwm waveforms v bat = 12 v, i out = 400 ma, f pwm = 200 hz 4 channels enabled, 6 leds each channel 50% pwm duty cycle (startup) 1% pwm duty cycle (startup) v pwm i out v out i bat t v pwm i out v out i bat t symbol parameter units/division c1 v pwm 5 v c2 v out 20 v c3 i out 500 ma c4 i bat 500 ma t time 100 ms c3 c3 c4 c4 c2 c2 c1 c1
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com soft start turn on using rising v bat v bat = 12 v, i out = 400 ma 4 channels enabled, 6 series leds each symbol parameter units/division c1 v bat 10 v c2 i bat 500 ma c3 v out 20 v c4 i out 500 ma t time 5 ms v bat c4 c2 c3 c1 i out v out i bat t a. v bat voltage slowly increased with en held high. a?b. input bulk capacitor c bat and boost output capacitor c out are charged to v uvlo . b. v bat reaches v uvlo , and enables A8501 through soft start. b?c. during soft start period, boost switch peak current is limited to 600 ma and led current to 1 / 20 of desired level. narrow current spike at b is due to parasitic capacitance from out to ground and c bias . comp pin is help low during soft start. d. after v out reaches a level such that all led pins > 0.75 v, the A8501 comes out of soft start. c?e. after initial rise of v out , the capacitor c comp starts charging slowly (c comp not shown). e. v comp reaches desired level for stable operation. f. A8501 and leds reach thermal steady state. a a b b c c d d e e f f turn on using en pin v bat = 8 v, i out = 400 ma 4 channels enabled, 6 series leds each symbol parameter units/division c1 v bat 5 v c2 v out 20 v c3 i out 500 ma c4 i bat 500 ma t time 2 ms v en c3 c4 c2 c1 i out v out i bat t performance characteristics startup waveforms
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com performance characteristics -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 0 102030405060708090100 pwm duty cycle (%) error (%) error (%) corrected error (%) with 2.5 s turn-on delay -6 -5 -4 -3 -2 -1 0 0 102030405060708090100 pwm duty cycle (%) error (%) error (%) corrected error (%) with 2.5 s turn-on delay 0 10 20 30 40 50 60 70 80 90 100 0 20406080100 pwm duty cycle (%) i led (ma) 100 hz 200 hz 80 81 82 83 84 85 86 87 88 89 90 0 102030405060708090100 pwm duty cycle (%) efficiency (%) 200 hz 100 hz pwm pwm the led current error graph shows the effect of pwm duty cycles on led current error, according to the relationship: error (%) = (i iset 960 x pwm duty cycle ? i led (av)) / (i iset 960 x pwm duty cycle) . at lower pwm duty cycles, turn-on delay adversely affects led current accuracy. this accuracy can be improved by extending the applied pwm signal by 2.5 s. for example, at 100 hz pwm and 1% pwm duty cycle, the on-time would be 100 s. the effects of that turn-on delay could be offset by applying a 102.5 s pwm pulse. led current error at 100 hz pwm led current error at 200 hz pwm led current versus pwm duty cycle efficiency versus pwm duty cycle
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com all four led strings disconnected simultaneously. v out increases to ovp level, and all led strings are removed from regulation. symbol parameter units/division c1 v bat 10 v c2 v out 20 v c3 v led1 1 v c4 i out 500 ma t time 100 s v bat v out v led1 i out t c3 c4 c2 c1 symbol parameter units/division c1 v bat 10 v c2 v out 20 v c3 v led1 1 v c4 i out 500 ma t time 100 s led string #1 disconnected. v out increases to ovp level, and led string #1 is removed from regulation. the rest of the led strings continue to function normally. v bat v out v led1 i out t c3 c4 c2 c1 performance characteristics output led open protection v bat = 12 v, i led = 100 ma per led string, en = high
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com performance characteristics iset characterization led current versus r iset 0 20 40 60 80 100 02030 30 50 50 70 90 10 10 40 60 70 i led (ma) r iset (k ) 0 0.02 0.03 0.01 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0 20 30 10 40 50 60 70 80 90 100 1/r iset (r iset in k ) i led (ma) led current versus 1/ r iset
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com disconnect switch overcurrent fault timing diagram a b c d e f g a b c d e f g t t t t t v en v sw i out v comp v cap 30 v 5 v 1 a 30 v 5 v v out a. overcurrent on disconnect switch is detected and disconnect switch latches off. boost is turned off when >3 v is detected across the disconnect switch. leds stop sinking current because there is insufficient voltage across them. b. comp pin reaches lockout level. leds are internally turned off and the comp pin is discharged. c. comp pin reaches ground voltage, leds are internally turned on, in soft start mode, and boost is put into soft start mode. boost and leds remain off because v out is still at ground potential due to the disconnect switch being latched off. d. user turns off en. e. the A8501 shuts down when en is off for more than 131,072 clock cycles. if any other fault conditions were present prior to shutdown, such as: open led, tsd, shorted led, or secondary ovp, these are now cleared and the part is ready to be re-enabled. f. user re-enables operation. A8501 enters soft start mode. g. soft start mode finished. performance characteristics
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com performance characteristics fault protection v bat = 12 v, i led = 100 ma per string 4 channels enabled, 8 series leds each vout to led1 short symbol parameter units/division c1 i out 200 ma c2 v cap 5 v c3 v out 5 v t time 1 s v cap c3 c2 c1 i out v out t v out to ground short v cap c3 c2 c1 i out v out t open schottky diode disconnect symbol parameter units/division c1 i out 200 ma c2 v sw 10 v c3 v out 5 v t time 20 s c3 c2 c1 i out t symbol parameter units/division c1 i out 1 a c2 v cap 5 v c3 v out 5 v t time 2 s v sw v out (led short detect activated, causing a latched shutdown) (output disconnect switch opens to prevent any damage) (secondary ovp activated, causing a latched shutdown)
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com description the A8501 is a multioutput wled/rgb driver for display back- lighting. it uses a boost converter architecture to generate output voltage to drive 4 channels with up to 9 leds per channel (v f = 3.5 v, i f = 100 ma). the current-mode boost converter operates at constant frequency. the boost switching frequency can be set from 600 khz to 2.2 mhz by an external resistor con- nected across fset and agnd. the integrated boost dmos switch is rated for 40 v at 3.6 a. this switch is protected against overvoltage, and provides pulse-by-pulse current limiting inde- pendently of boost converter duty cycle. the A8501 has 4 well-matched current sinks, which provide regulated current through the load leds for uniform display brightness. all ledx sinks are rated for 21 v to allow pwm dimming control. frequency selection the switching frequency on the sw pin, f sw , can be set by applying the following equation: f sw = 51 / r fset , (1) where f sw is in mhz, and r fset is in k . led selection which led strings are enabled is determined by the combined settings of the sel1 and sel2 pins, according to the following table: led channel selection sel1 pin sel2 pin enabled ledx outputs low low only led1 high low led1 and led2 low high led1, led2, and led3 high high all channels led strings that are connected to the A8501, but are not enabled through the selx pins, may cause a shutdown if the voltage on the corresponding ledx pins exceeds v ledsc . refer to the led short detect section for further details. unused ledx pins can be left open or connected to ground. use matched forward voltage leds for better efficiency. the application circuit shown in figure 1 is a boost converter and the output voltage is always higher than the battery volt- age. therefore, the quantity of leds per string should be such that the required output voltage is higher than the maximum battery voltage. if the battery voltage is higher than the output voltage, the A8501 will switch with minimum pulse width, and the actual output voltage will be higher than the required volt- age. the excess voltage will be dropped across the led strings. this lowers efficiency and increases power dissipation, resulting in higher device temperature. if battery voltage must be higher than required output voltage, use a sepic converter, as shown in figure 10. soft-start and compensation at startup, the output capacitor is discharged and the A8501 enters soft start. the boost current is limited to 0.6 a and all active ledx pins sink 1 / 20 of the set current until all the enabled ledx pins reach 0.75 v. when the A8501 comes out of soft start, the boost current and the ledx pin currents are set to normal. the output capacitor charges to voltage required to sup- ply full ledx currents within a few cycles. once v out reaches the required level, ledx current toggles between 0 and 100% in response to pwm signals. soft start behavior on evaluation boards is shown in the performance characteristics section. functional description
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com led current setting the maximum led current can be up to 100 ma per chan- nel, and is set through the iset pin. connect a resistor, riset, between this pin and agnd to set the reference current level, i iset , according to the following formula: i iset = 1.235 / r iset , (2) where i iset is in ma and r iset is in k . this current is multiplied internally with a gain of 960, and mir- rored on all enabled led pins. this sets the maximum current through the leds, referred as the 100% current . dimming the led current can be reduced from the 100% cur- rent level by three alternative dimming methods: ? pwm dimming using the en pin. pwm dimming is performed by applying an external pwm signal on the en pin. when the en pin is pulled high, the A8501 turns on and all enabled leds sink 100% current. the sequence is shown in figure 2. for optimal accuracy, the external pwm signal should be in the range 100 to 300 hz. the slight delay between pwm signal and the led current causes an error. to compensate for the error, a small turn-on delay should be added to the pwm signal as shown on page 10 of the performance characteristics section. when en is pulled low, the boost converter and led sinks are turned off. the compensation (comp) pin is floated, and criti- cal internal circuits are kept active. if en is pulled low for more than t pwml , the device enters shutdown mode and clears all internal fault registers. as an example, for a 2 mhz clock, the maximum pwm low period while avoiding shutdown is 65 ms. ? analog dimming using the dim pin. when the dim pin is pulled low, the led sinks draw 100 % current; when the pin is pulled high, the led current level drops to 25%. ? analog dimming using the vti pin. external dc voltage can be applied to the vti pin to control led current. led current var- ies as a function of voltage on the vti pin. this configuration is shown in figure 5. led open detect when any led string opens, the boost circuit increases the output voltage until it reaches the overvolt- age protection level. the ovp event causes any led string that is not in regulation to be locked-out from regulating the loop. by removing the open led from controlling the boost, the output voltage returns to normal operating voltage. every ovp event retests all led strings. an en low signal does not reset the led string regulation lock unless it shuts down the device (exceeds t pwml ). the locked-out led pins always attempt to sink desired current regardless of lock-out state. led short detect any led pin that has a voltage exceed- ing v ledsc will force the device to disable the boost circuit and ledx outputs until en shuts down the A8501 (en low exceeds t pwml ). this protects the ledx pins from potentially hazardous voltages when multiple leds are shorted in one string. overvoltage protection the A8501 has overvoltage pro- tection (ovp) and open schottky diode protection. the ovp has a default level of 19.5 v and can be increased up to 38 v by the selection of an external resistor, as shown in figure 3. when the current though ovp pin exceeds 200 a, the ovp comparator goes low. when v out falls and current through the ovp pin drops below 165 a, the ovp is released. 1.23 v 18 v sw sw ovp rovp d1 v out v batt cout A8501 ovp disable sw + ? 1.23 v + ? latch figure 3. overvoltage protection (ovp) circuit figure 2. timing diagram of external pwm signal and led current 0 ma external pwm signal en i ledx turn-on delay 100% current
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the following equation can be used to determine the resistance for setting the ovp level: r ovp = (v ovp ? 19.5) / 200 a , (3) where v ovp is the target typical ovp level, and r ovp is the value of the external resistor, in . A8501 has secondary overvoltage protection to protect internal switches in the event of an open diode condition. open schottky diode detection is implemented by detecting overvoltage on the sw pin. if voltage on the sw pin exceeds the device safe operat- ing voltage rating, the A8501 disables and remains latched. the ic must shut down before it can be reenabled. overcurrent protection the boost switch is protected with pulse-by-pulse current limiting at 3.6 a. the output disconnect switch protects against output overcurrent. at 1 a typical, the A8501 disables. this process is detailed in the disconnect switch overcurrent fault timing diagram in the performance character- istics section, page 13. in some instances, when the leds are connected by long wires and also some output capacitance (such as esd capacitors) is present, a clamping diode on the output must be used. this diode will prevent the output from momentarily going negative during a short circuit condition. the diode must be chosen such that its reverse breakdown voltage is higher than normal operating volt- age and its reverse current leakage is small. please refer to the application note output diode clamping for the A8501 for more details. input uvlo when v in rises above the uvlo enable hyster- esis (v uvlo(th) + v uvlo(hys) ), the A8501 is enabled. it is disabled when v in falls below v uvlo(th) for more than 50 s. this lag is to avoid shutting down because of momentary glitches in the power supply. input ovlo when v in rises above v ovlo(th) for more than 50 s, the A8501 is disabled, the boost converter shuts down instantly, and led current falls gradually with the cap pin capacitor. when v in falls below v ovlo(th) and en is high, the device is reenabled. thermal derating thermal derating can be achieved by con- necting an ntc thermistor between vti and ground, as shown in figure 5. when the A8501 is enabled and v ti > 1.1 v, 100% cur- rent for the leds is controlled by the iset and dim pins. this is represented by the solid blue curves in figure 6. when v ti falls below 1.1 v, v iset starts to follow v ti , resulting in i ledx varying proportionately with v ti represented by the overlap of the dotted and solid curves. the proportion of i led to v ti , when led cur- rent is controlled through the vti pin, is calculated as: i iledx = 960 v ti / r iset , (4) where i ledx is the ledx pin current in ma, and r iset is in k . there is a hysteresis built into the vti pin circuit, so while v ti is decreasing, there is a delay before proportional change begins if vti pin voltage starts above 1.1 v, as shown by the solid blue curves in figure 6. when v ti starts below 1.1 v, or falls below 1.1 v during operation and then starts increasing again v iset will follow v ti until the voltage reaches 1.23 v as shown by the red- and-white dotted curves in figure 6. figure 5. thermal derating reference circuit vto vti ntc riset rvc A8501 ?t iset led current reference + ? minimum select 2.46 v 1.23 v 2 figure 4. output overvoltage protection (ovp) operation i led t symbol parameter units/division c1 v ovp 10 v c2 i led 50 ma t time 100 s c2 c1 v ovp
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com i led versus v ti at t a = 125c i led versus v ti at t a = 25c i led versus v ti at t a = ?40c 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 v ti (v) v ti (v) v ti (v) i led (ma) i led (ma) i led (ma) 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 v ti decreasing v ti increasing v ti decreasing v ti increasing v ti decreasing v ti increasing figure 6. ledx current versus v ti (a) (b) (c)
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com bias supply the bias pin provides regulated 6 v for internal circuits. con- nect a cbias capacitor with a value in the range of 0.1 to 1 f. efficiency considerations for better efficiency, use a high quality inductor with relatively low dcr and core loss. use a low forward voltage schottky diode with relatively low junction capacitance. use matched forward voltage leds for better efficiency. the A8501 provides an output disconnect function through a load switch that is connected from the boost converter output (cap) to led connection (out). this function protects the system against short circuit conditions from common anode led connection to ground, for both boost and sepic configurations. when comparing the efficiency of the A8501 with an alternate implementation requiring an external input/output disconnect function, the additional power dissipation in this disconnect switch must be considered for a proper comparison. to bypass the disconnect switch, short the cap pin to the out pin to have a direct connection from the boost regulator to the com- mon anode led node. when the disconnect switch is bypassed, both the boost and the sepic implementations are not protected against output short circuit conditions. audible noise considerations multilayer ceramic capacitors cause audible noise when sub- jected to voltage ripple in the audio frequency range, due to the piezoelectric effect. ceramic capacitors connected across boost converters can also cause audible noise due to voltage ripple at dimming frequencies. during the pwm dimming off-time, the voltage across the capacitors drops due to leakage through the output disconnect switch and the ovp pin. this voltage is regulated to the desired output level during the pwm dimming on-time. this voltage ripple may cause audible noise. audible noise can be minimized with higher dimming frequency, but at higher dimming frequencies accuracy may be affected, as shown in the performance characteristics section. it is recom- mended to use 200 hz for optimum performance. selecting a sufficiently large capacitor across the boost output can reduce voltage ripple and noise. it is observed that the audible noise below 250 mv ripple is negligible. the value to select for a boost capacitor can be calculated using the following formula: c . 0.25 f pwm (1 ? d fpwmmin ) i lk (5) where i lk is the leakage current; select i lk = 165 a at a 30 v output and 175 a at a 40 v output, d fpwmmin is the minimum dimming pwm duty cycle, and f pwm is the dimming frequency; typically 200 hz. for example, if the dimming frequency is 200 hz, the minimum dimming pwm duty cycle = 10%, and v out = 30 v, then select the boost capacitor as: c 3 f == . 0.25 200 (1 ? 0.1) 165 a the capacitance of ceramic capacitors drops with dc bias. use an appropriate capacitor to get at least 3 f at 30 v. the selection of a ripple voltage of 0.25 v is based on a typical mlcc. this ripple level depends on the type and construction of the mlcc. increase the boost capacitor if noise exists at 0.25 v.
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application information design example this section provides a method for selecting component values when designing an application using the A8501. assumptions for the purposes of this example, the following are given as the application requirements: ? v bat : 8 to 18 v ? quantity of led channels, # channels : 3 ? quantity of series leds per channel, # seriesleds : 8 ? led current per channel, i led : 80 ma ? total current all channels, i out = i led # channels ? v f at 80 ma: 3 to 3.4 v ? f sw : 2 mhz ? t a (max): 65c dimming the A8501 can work with wide range of pwm fre- quencies. a small delay between the pwm signal and the led current may have a noticeable effect at high pwm frequencies combined with low pwm duty cycles. for example, at 100 hz and 10% pwm duty cycle, the pwm on-period is 1 ms. in that period, the delay causes only a 0.6% error. if the pwm frequency is 1 khz, this error is 6%. however, the error caused by the turn- on delay can be decreased by increasing the applied pwm duty cycle as shown on page 10 in the performance characteristics section. procedure the procedure consists of selecting the appropriate configuration and then the individual component values, in an ordered sequence. 1. identify the sel x pins to use. for 3 channels: ? connect pin sel2 to v to ? connect pin sel1 to ground 2. connect leds to pins led1 through led3 (leave pin led4 open). 3. select resistor riset (connected between pin iset and agnd). given i led = 80 ma and a iset = 960, then: r iset = 1.235 / (i led / a iset ) . (6) substituting: r iset = 1.235 / (0.080 / 960) = 14.82 k . select a common value: 14.7 k , 1%. 4. select resistor rfset (connected between pin fset and agnd). given: r fset = 51 /f sw , (7) for a 2 mhz switching frequency, select: r fset = 51 / 2 = 25.5 k , 1%. 5. select resistor rovp (connect to the ovp pin to set the ovp level, v out (max)). given v f (max) = 3.4 v, 0.75 v as the v led regulation level, and worst case output disconnect switch voltage drop, then: v out (max) ( v f (max) # seriesleds ) + v led + ( r ods(on) i led # channels ) = . (8) substituting: v out (max) = (3.4 8 + 0.75) + (4 0.08 3) = 28.91 v . the switch resistance r ods(on) can be found in the electri- cal table and is listed as worst case at 4 at high tempera- tures. to set the output ovp level to 33 v, given an i ovph of 200 a, and v ovp(th) = 19.5 v: r ovp = ( v ovp ? v ovp(th) ) / i ovph . (9) substituting: r ovp = (33 ? 19.5) / 200 10 -6 = 68 k . (10) 6. select inductor l1. this should assume a maximum boost converter duty cycle, d(max), at v bat (min) and 90% ef- ficiency, . d (max) = 1? ( v bat (min) ) / v out (max) (11) d (max) = 1? (8 0.9) / 28.91 = 75% . then calculate maximum switch on-time: t on (max) = d(max) / f sw (12) = 0.75 / 2 10 6 = 375 ns . maximum input current can be calculated as: i bat = ( v out (max) i out ) / ( v bat (min) ) (13) i bat (max) = [28.91 (0.080 3)] / (8 0.9) = 963 ma.
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 21 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com set inductor ripple at 30% of i bat (max): i l = i bat (max) i lripple (ideal) . (14) substituting: ? i l = 0.3 963 = 289 ma . given, during switch on-time: v bat (min) = l ? i l f sw / d , (15) 8 = l 0.289 2 10 6 / 0.75, and l = 10.4 h . select a common value: l (used) = 10 h. it is recommended to select an inductor that can handle a dc current level that is greater than 963 ma, at the peak current level (saturation) of 963 ma + 289 ma / 2 = 1.11 a. this is to ensure that the inductor does not saturate at any steady state or transient condition, within specified temperature and tolerance ranges. inductor saturation level decreases with increasing temperature. it is advisable to use a inductor with a saturation level of 2.0 a. the inductor should have a low dc resistance (dcr) and core loss for better efficiency. 7. select output capacitor cout, given: f pwm = 100 hz , (16) assuming 20% minimum dimming pwm duty cycle, d pwm(min) , and the maximum leakage current through the output disconnect switch at v out = 28 v is 165 a and v coutripple = 0.25 v. select the output capacitor as: c out = i lk (1 ? d pwm(min) ) / ( f pwm v coutripple ) . (17) substituting: c out = 165 a (1 ? 0.2) / (100 0.25) = 5.3 f . (18) select 6.8 f. the rms current through cout is given by: c rms 1 / 2 i out = , ? ? ? ? ? ? ? ? 1? d d (max) + ( r / 12) (19) where: r = i l / i bat (max) , and (20) ? i l = . ? ? ? ? ? ? ? ? ? l (used) f sw v bat (min) d (21) substituting: (80 ma 3 ) {[0.75 + (0.3 / 12)]/(1?0.75)} 1/2 = 0.422 a . select a capacitor with an rms current rating greater than 0.422 a. 8. select input capacitor cin, given: c in = ? i l / (8 f sw ? v inripple ) , (22) where ? v inripple is the input ripple voltage, which can be as- sumed to be 1% of v bat . then: c in = 0.3 / (8 2 10 6 0.01 8) = 0.23 f . select a 2.2 f or higher, 35 or 50 v, ceramic capacitor, x5r or x7r grade. the rms current through cin is given by: i inrms = ( i out r ) / [(1 ? d ) 12 1/2 ], (23) = [(80 ma 3 ) 0.3] / [(1 ? 0.75) 3.46] = 83 ma . select a capacitor with an rms current rating greater than 83 ma. 9. select the boost diode d1 (connect between the sw pins and the output). d1 should be a schottky diode with low forward drop and junction capacitance. the diode reverse voltage rating should be greater than v out . a 40 to 50 v diode rating is recommended. the diode dc current rating should be greater than i out and the peak repetitive current rating should be > i bat (max) + ? i l / 2. 10. select the compensation capacitor ccomp (connect between the comp pin and ground). typically, use a 1 f capacitor to reduce audio hum during pwm dimming. 11. calculate power loss. calculate power loss at various operat- ing conditions to estimate worst-case power dissipation. a) loss in led drive: i ledx v ledx for one string + ( i ledx v ledx (av) +0.75 quantity of remaining enabled led strings), (24) where v ledx is the regulation voltage of the ledx pins, 0.75 v typical, and worst-case drop is mismatch due to led v f . a good approximation for v ledx (av) is 0.8 v. this assumes that some of the remaining strings will regulate below, and some above, a value of 1.55 v. if the predicted led match- ing is tighter, then a lower value can be used. if the predicted led mismatch is large, then a higher value should be used. to get the complete and accurate power dissipation, the user will need to measure each individual led pin to get the exact v led voltage: (80 ma 0.75) + [80 ma 2 (0.8 + 0.75)] = 0.308 w .
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 22 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com b) loss in low drop-out regulator (ldo) + bias: p ldo = v bat (max) i bias , (25) with bias current during switching 17 ma typical. c) boost switch conduction loss: i 2 bat (max) d r ds(on) (1+ r 2 /12) , (26) where: r = i l / i bat (max) . (27) d) boost switch switching loss: v out i bat (max) ( t rise + t fall ) f sw . (28) switch loss calculations assume negligible input gate charge on internal boost mosfet until v g(th) (gate threshold), com- pared to the miller charge; t rise and t fall are measured in the lab under full load conditions. to approximate this value, use 5 ns for rise and fall times. e) diode loss: diode switching loss = 0.2 c d v 2 out f sw , (29) where c d is the average junction capacitance of the schottky diode. then: diode conduction loss = v f i bat (max) (1? d ) (30) f) inductor dcr loss: i 2 in r dc (1+ r 2 /12) . (31) g) inductor core loss: this value is an estimate. the default value would be 50 mw at 1 a ripple current, and then scaled based on ripple current. h) power loss in output disconnect switch: p swdisc(on) = r ods(on) i out 2 , (32) if the output disconnect switch on-resistance, r ods(on) , is 2 , then: p swdisc(on) = 2 0.24 2 = 0.11 w .
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 23 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com en fset nc vto vti comp iset riset rntc rvc cin d1 l1 10 h vin sw sw sw ovp cap out rovp v bat 8 to 21 v A8501 led4 led3 led2 led1 dim sel1 sel2 bias ?t ccomp 1 f 10 v cbat 4.7 f 50 v cout 4.7 f 50 v cbias 0.1 f 10 v dgnd lgnd agnd pgnd pgnd pgnd rfset 25.5 k 12.4 k pad figure 7. typical circuit for driving 2 led strings at up to 35 v at 200 ma per led string, with thermal derating typical application circuits en vto vti iset dac d1 l1 10 h vin sw sw sw ovp cap out rovp v bat 8 to 21 v A8501 led4 led3 led2 led1 cin cbat 4.7 f 50 v cout 4.7 f 50 v comp dim ccomp 1 f 10 v fset nc sel1 sel2 bias cbias 0.1 f 10 v riset dgnd lgnd agnd pgnd pgnd pgnd pad rfset 25.5 k 24.3 k figure 8. typical circuit for analog dimming with external dc voltage en iset d1 l1 10 h vin sw sw sw ovp cap cp1 cp2 cp3 cp4 out rovp v bat 8 to 21 v A8501 led4 led3 led2 led1 cin cbat 4.7 f 50 v cout 4.7 f 50 v fset nc vto vti comp rntc rvc dim sel1 sel2 bias ?t ccomp 1 f 10 v cbias 0.1 f 10 v riset dgnd lgnd agnd pgnd pgnd pgnd pad rfset 25.5 k 24.3 k figure 9. typical circuit with esd capacitors across leds (cpx 10 nf), with thermal derating en vto vti iset d1 l1 10 h l2 10 h vin sw sw sw ovp cap out rovp v bat 8 to 16 v A8501 led4 led3 led2 led1 cin cbat 4.7 f 50 v cout 4.7 f 50 v cc 1 f 50 v comp dim ccomp 1 f 10 v fset nc sel1 sel2 bias cbias 0.1 f 10 v riset dgnd lgnd agnd pgnd pgnd pgnd pad rfset 25.5 k 24.3 k figure 10. typical circuit as sepic converter (sepic converters can provide output voltage higher or lower than the input voltage; this topology can be used if the required output voltage level is within application input voltage range)
2 mhz, 4 channel100 ma wled/rgb driver with output disconnect A8501 24 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 28-pin tssop with exposed thermal pad copyright ?2008-2010, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 28x 0.65 bsc 0.25 bsc 2 1 28 9.700.10 4.400.10 6.400.20 gauge plane seating plane a terminal #1 mark area b for reference only; not for tooling use (reference mo-153 aet) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b c exposed thermal pad (bottom surface); dimensions may vary with device branded face 6.10 0.65 0.45 1.65 3.00 5.00 28 2 1 pcb layout reference view c 5.08 nom 3 nom reference land pattern layout (reference ipc7351 sop65p640x120-29cm); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5)

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